Aravind. M

About Aravind. M

ASIC/IP/SubSystem Design Verification engineer with around 6.5 years of VLSI Industry experience.Experienced in developing testbenches from the scratch, experienced in developing verification components ( Env, Tests, Scoreboard) using System Verilog and UVM methodology.Experienced in developing verification plan and test plan for complex scenarios Hands on experience in IP verification ( Both Unit level and top level) from the scratch.Knowledge in PCIe(TLP),AMBA AXI,APB,AHB,UART, SPI, I2C protocols. Well versed in coverage closure, assertions and constrained random stimulus testing.Experienced in different scripting languages like Python,Shell.Automated RAL register library and register block generation with the help of python based scripting.Hands on experience in Synopsys simulation tools like VCS,Verdi,DVE and Cadence simulations tools like Excelium, simvision and integrated metrics center (IMC) for functional and code coverage analysis.

Experience

1. Sr Silicon Design Engineer

   AMD

   Jul 2022 — Present

   SS level verification of a major subsystem in GPU pipeline Verification of RISC-V processor.

Education

• NSS College of Engineering, Palakkad

  Bachelor of Technology (B.Tech.), Instrumentation and Control Engg.

  2009 — 2013

• Sandeepani School of VLSI Design

  PG diploma, VLSI Design and Verification

  2017 — 2018

• College of Engineering Trivandrum

  M.Tech, Micro and Nano Electronics(VLSI)

  2015 — 2017