Arash Talebi

WORK HISTORY

EDUCATION

SKILLS

ABOUT ARASH TALEBI

Experienced in ASIC and FPGA design, from top-level system specifications down to RTL coding (System Verilog, Verilog, VHDL), simulation, synthesis, implementation, timing analysis and experienced in low power design methodology (CPF/UPF)• Fully familiar with PCIE/CXL, NVMe, and SAS protocols. • Familiar with Formal verification (FPV) and experienced with spyglass tool using for clock gating efficiency (SEC) and linting.• Familiar with Power Artist tools (PA) used for power efficient ASIC design. • Familiar in block level, subsystem level and chip level verification with System Verilog and Universal Verification Methodology (UVM)• Experienced in defining block level Micro-Architecture-Specification (MAS) and defining system level Specification and Requirements.• Design Experience with Xilinx ISE – Synthesis, Optimization, Place and route• Hands-on experience with research and development of mobile broadband technologies such as LTE/LTE-A and WiMAX/WIFI including PHY, MIMO/OFDM systems, MAC layer and upper layer algorithms and architecture • Experienced in Using test Equipment- PCIE analyzer, Oscilloscope, Spectrum Analyzer• Strong programming and design skills (Python, C/C++, Perl, TCL, AWK, Linux, MATLAB)• Excellent background in Telecommunications, Signal Processing and Mathematics and power optimization • Proven problem-solving, fast-learning, multi-tasking and team-involvement abilities • Strong analytical skills and eager to find innovative solutions to problems• Excellent communication, presentation and interpersonal abilities, highly motivated to work independently or as a part of team within a learning environment