Arash N.
Msip Emc Design Engineer @恩智浦半導體
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WORK HISTORY
Msip Emc Design Engineer @恩智浦半導體
Munich, DE
As a Development EMC Design Senior Engineer at NXP Semiconductors in Munich, I am responsible for driving the full lifecycle development of EMC/EMI-robust analog and mixed-signal (AMS) IP for automotive SoCs and ASICs—from concept and system architecture through circuit design, verification, silicon bring-up, and characterization. My work spans the ownership of complex AMS subsystems, including sensor-interface and signal-conditioning circuitry, data-conversion IP (Sigma-Delta and Nyquist-rate ADCs/DACs), and power-management blocks such as regulators, supply supervision, and protection circuits. I design and validate EMC-optimized test boards for advanced AMS IP, perform detailed signal-integrity and EMC simulations (impedance, crosstalk, EMI scanning), and develop mixed-signal verification strategies to ensure robustness in environments with high-speed digital and sensitive analog/RF domains. In addition, I provide technical leadership and guidance to analog, digital, and layout teams to ensure EMC-aware implementation across the design flow, and I conduct hands-on post-silicon EMC testing and diagnostics to validate compliance with automotive standards and drive continuous improvement.
EDUCATION
Leibniz Universität Hannover
PhD
OLCI construction college
City and guild elector-technical technology
University of Bath
Master of Engineering (MEng)
Azad University (IAU)
Higher national Diploma (HND)
ABOUT ARASH N.
I am an Member and multidomain engineer with deep expertise in Electromagnetic Compatibility (EMC/EMI), Analog & Mixed-Signal design, and Power System Engineering, with over a decade of experience spanning the automotive semiconductor industry, embedded systems, smart grid research, and UK high-voltage transmission networks. My career has uniquely positioned me at the intersection of circuit design, signal integrity, EMC verification, power systems analysis, and statistical risk modelling.At NXP Semiconductors, I lead the development of EMC-robust analog and mixed-signal IP for automotive SoCs—covering concept development, AMS design, verification, SI/PI analysis, post-silicon EMC validation, and test-board design. Prior to this, I drove EMC certification and board-level design improvements at Avnet Embedded, supporting medical, industrial, and automotive applications.During my PhD at Leibniz University Hannover and the German Military Research Institute (WIS), I specialized in smart-grid EMI risk analysis, developing stochastic and Monte-Carlo-based methods to quantify system-level electromagnetic vulnerabilities—supported by extensive experimentation, Python-based modelling, and automated measurement systems.My earlier experience includes roles in power system design and control system modelling at National Grid UK, and distribution network consultancy at Burns & McDonnell, where I performed network studies, grounding design, harmonic analysis, SCADA/IEMS model updates, and HV transmission connection assessments.I bring strong hands-on competence with EMC test equipment, RF/microwave tools, PCB/IC design flows, numerical EM simulation (CST, HFSS), SI/PI analysis, PowerFactory/PSCAD, and a wide range of risk-analysis methodologies. I am passionate about building robust high-frequency and high-voltage systems, solving complex EMC challenges, and driving technically rigorous design practices across multidisciplinary engineering teams.
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