Appu Sajeev
SoC Design Engineer at Intel Corporation
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Appu Sajeev
10+ years of professional experience at Intel Corporation (Bangalore, India) primarilyfocussing on server cpu rtl performance verification with career aspirations in cpuperformance/architecure/microarchitecture.Currently, hands-on leading a 6 member performance val team, responsible for ensuring that the system level rtl performance goals (bandwidth, latency) of the nextgen Xeon server cpu being built is met in pre-silicon simulation environment.
Experience
Soc Design Engineer
Dec 2015 — Present · Bengaluru, IN
Working on the SoC level performance verification of the next generation of Intel Xeon Server SoCs. This includes activities starting from performance studies on the cycle accurate performance model to the simulation based performance verification of the actual functional RTL CPU model. RTL level activities involve performance parameter correlation (cache/memory/io (pcie) latency, bandwidth), analytical performance studies of underlying interconnects, tuning of SoC parameters (eg: buffering/credits), debug and resolution of performance shortfalls/inversions etc.The job role have given me an in depth understanding and perspective of SoC performance and the x86 system architecture development process from step one. The job role has also given me an intimate understanding of RTL simulation based functional verification process/environment.
Education
Government Engineering College, Thrissur
Bachelor's degree, Computer Science
2007 — 2011
National Institute of Technology Calicut
Master of Technology (M.Tech.), Computer Science
2011 — 2013
Skills
- System Verilog
- System on a Chip (Soc)
- Systemverilog
- Shell Scripting
- Linux
- Debugging
- Interconnects
- Xeon Architecture
- Mysql
- C
- Perl
- Cache Coherency
- Intel Qpi Protocol
- X86 Assembly
- Algorithms
- Git
- C++
- Python
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