Appala Naidu Ponnada
Sr Design Engineering Manager at Cadence Design Systems || Ex-Intelite
- Role
- Sr Design Engineering Manager at Cadence
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Appala Naidu Ponnada
Semiconductor Professional with 8+ years of experience in RTL2GDS Physical design and implementation. Skilled in all aspects of RTL to GDS flow with expertise in RTL synthesis, Low power P&R implementation, SignOff Methodologies on industry standard tools.Extensively worked to develop backend CTS Methodologies on Cadence and Synopsis tools. I have strong knowledge on Semiconductor device physics and digital circuits. Developed a flexible electronic circuit on Paper substrate using Organic Thin Film Semiconductor Materials.
Experience
Sr Design Engineering Manager
Apr 2025 — Present · Hyderabad, IN
Responsible for physical design and implementation of Cadence IPs.
Education
Indian Institute of Technology, Kanpur
Master of Technology - MTech, Microelectronics and VLSI design
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