Aparna Agrawal
IIT Bombay EE\'26 | Hardware Intern at Qualcomm
- Role
- Hardware Engineering Intern at Qualcomm
- Location
- Kanpur, IN
- LinkedIn followers
- 500 followers
About Aparna Agrawal
Hi! I\'m Aparna Agrawal, an undergraduate student at the Indian Institute of Technology Bombay, currently pursuing my degree in Electrical Engineering along with a minor in Data Science and Artificial Intelligence. I\'m passionate about digital design, VLSI systems, and everything that brings complex hardware to life. My interests lie at the intersection of hardware architecture and system-level design. I\'ve worked on a variety of hands-on projects, including the design of a 2-way out-of-order superscalar processor, a 6-stage pipelined microprocessor, and image compression/decompression using wavelets on chip. Through these, I’ve gained practical experience in VHDL/Verilog, RTL simulation, and ASIC design flows using tools like Cadence Innovus, OpenLane, GHDL, and GTKWave. I enjoy solving challenges related to timing, performance, and power, and I\'m excited by the prospect of building efficient and intelligent digital systems from the ground up. Always up for a good conversation on processors, digital logic, or silicon design. Feel free to connect at a••••••••@gmail.com!
Experience
Hardware Engineering Intern
May 2025 — Present · Hyderabad, IN
Education
Indian Institute of Technology, Bombay
Dual degree
2021 — 2026
Indian Convent School
Class 12th
St. Mary's Convent High school
Class 10
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