Aditya Pagonda
Senior Principal Engineer @Arm
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WORK HISTORY
Senior Principal Engineer @Arm
Cambridgeshire, GB
EDUCATION
University of Mumbai
B.E, Electronics Engineering
Indian Institute of Technology, Bombay
Final Year Project
SKILLS
ABOUT ADITYA PAGONDA
ASIC Verification professional with 16+ years of semiconductor industry experience. Strong expertise in verifying complex designs, setting up methodologies, architecting testbenches, building and leading verification teams. Good experience on latest tools & verification methodologies. Have a pragmatic view to solving problems. Prior experience at Broadcom, ST Microelectronics, ARM, LSI & start-ups.Specialties: Verilog, System Verilog, ABV, Coverage driven verification using RVM, OVM, UVM, custom base class infrastructure. Developed re-usable verification IPs, Developed testbench architectures for IPs and SOC for video, storage and consumer chips.
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