Anwesha Acharjya
M.tech - VLSI DESIGN VIT VELLORE || VIT’26 || Intern @intel
- Role
- Graduate Technical Intern at Intel
- Location
- Kolkata, WB, IN
- LinkedIn followers
- 500 followers
About Anwesha Acharjya
Presently interning at Intel while pursuing an M.Tech in VLSI Design at VIT, Vellore. Dedicated to continuous learning and applying academic expertise to deliver impactful results within Intel. Presently occupied with HSIO group FE RTL team and working on RTL quality checks ( LINT, CDC, LP ) and FE BE handoff including IPQC, reviewing violations and reporting back to IP Design owners.Owning packaging of IP RTL and releases to BE. Additionally own the gatekeeper checks for lib view releases to verify presence of all views pertaining to SCAN/test integration at customer end. An aspiring Engineer with the dedication and technical acumen to contribute in the VLSI technology industry where I can develop and hone my skillsets and apply in real world problems to solvecomplex challenges. Good understanding of the VLSI design flow starting from spec to RTL to physical implementation to Silicon.A fluent communicator with the tenacity to hang onto complex debugs and bring the best out of myself in challenging situations.
Experience
Graduate Technical Intern
Jul 2025 — Present · Bengaluru, IN
Education
West Bengal University of Technology, Kolkata
Bachelor of Technology - BTech, Applied Electronics and Instrumentation Engineering
Vellore Institute of Technology(Vellore)
M.TECH , VLSI
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.