Anusha Prakash
Power, Noise and Reliability Specialist
- Role
- Cpu Implementation Engineer at Apple
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Anusha Prakash
Strong technical and business acumen in Power-Noise-Reliability space with hands-on experience in different SoC architectures operating in latest technology nodes. Skilled in working in a fast paced multi-customer-driven environment. Pre-sales and post-sales experience with several semiconductor companies.
Experience
Cpu Implementation Engineer
Jan 2020 — Present
Education
Stony Brook University
Master of Science (MS), Electrical and Electronics Engineering
2012 — 2013
MES Kishore Kendra
12th, PCMB
2006 — 2008
Sri vani education center
High School
2003 — 2006
Global Academy of Technology
Bachelor of Engineering (B.E.), Electronics and Communication Engineering
2008 — 2012
Skills
- Verilog
- Pspice
- Vhdl
- Simulations
- Circuit Layout
- Computer Architecture
- Rtl Coding
- Low-Power Design
- Pathfinder
- Cadence Virtuoso Layout Editor
- Synopsys Tools
- Totem
- C++
- Vlsi
- Hardware in the Loop Verification
- Modelsim
- Synopsys Design Compiler
- Active-Hdl
- Cadence
- H-Spice
- Cadence Virtuoso
- Digital Circuit Design
- Cadence Schematic Capture
- Managing Business Growth
- Altera Quartus
- Cadence Spectre
- Perl
- Eda
- Perl Script
- C/C++
- Rtl Verification
- Ubuntu
- Mixed Signal
- Reliability
- Ic Layout
- Nanotechnology
- Red Hat Linux
- Ic Station
- Systemc
- Fpga
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