Anush Shetty
Senior Physical Verification Engineer
- Role
- Senior Physical Verification Engineer at AstraSilica Technologies
- Location
- Mangaluru, KA, IN
- LinkedIn followers
- 500 followers
About Anush Shetty
Expertise in Innovus, Calibre, Fusion Compiler •Skilled in ensuring design integrity and meeting stringent quality standards in advanced tech nodes.•Passionate about optimizing workflows and delivering high-quality solutions in physical design verification. •Perform block level physical verification and work with the physical design team to close design issues like DRC/LVS/RV/antenna/density violations and sign off PV for tapeouts • Tapeout experience with good understanding of latest process nodes (7nm,5nm,4nm,3nm,2nm) • Good understanding of industry standard tools for place and route and tape out flows. • Good knowledge in scripting languages like Tcl,Perl • Feedback to block level and top level physical design engineers on key fixes required for Interface related issues. • Good hands on knowledge on EDA tools like Synopsys FC,ICV,ICC-II, Innovus. Actively looking for an opportunity to utilise the skills that I have acquired in the course of my studies along with gaining some more experience in the industry and in turn contribute towards the growth of an organisation as well as my career progression. Looking forward to learn more about the emerging technologies.
Experience
Senior Physical Verification Engineer
Nov 2024 — Present
Client :Qualcomm ( Nov 2024 - Nov 2025)AMD ( Dec 2025 - till date)
Education
St. Joseph College of Engineering
Bachelor of Engineering, Electronics and Communications Engineering
2016 — 2020
RV-VLSI and Embedded Systems Design Center
Advanced Diploma in ASIC design - Physical Design, Electrical, Electronics and Communications Engineering
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