Anurag T.
- Role
- Soc Design Engineer at Intel
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Anurag T.
Experienced in EDA, physical design.(Floorplan to tapeout) Taped-out several…
Experience
Soc Design Engineer
May 2022 — Present
Education
Jawaharlal Nehru Technological University
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering
2008 — 2012
San José State University
Master's degree, Electrical and Electronics Engineering
2013 — 2015
Skills
- Modelsim
- Standard Cell
- Vlsi
- Cadence Genus
- Microsoft Office
- C
- Rtl Design
- Edi
- Cadence Encounter
- Place & Route
- Microsoft Word
- Physical Design
- Tcl
- Multisim
- Gate Level Simulation
- Cadence
- Verilog-a
- Static Timing Analysis
- Cadence Spectre
- Pspice
- Vhdl
- Verilog
- C Language
- Xilinx Ise
- Perl
- Microsoft Excel
- Matlab
- Rtl Verification
- Cadence Rc
- Keil
- Data Structures
- Embedded C
- Unix
- Cadence Tempus
- Linux
- Fpga
- Cadence Innovus
- Cadence Virtuoso
- Synopsys Tools
- Wireshark
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