Anurag Jain
ASIC Physical Design | Semiconductor
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Anurag Jain
Hands on experience in semi-custom ASIC chip design flow and leading a Physical…
Experience
Soc Design Engineer
Jun 2021 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master of Technology - MTech, Microelectronics
2017 — 2019
Rajiv Gandhi Prodyogiki Vishwavidyalaya
Bachelor of Engineering (BE), Electronics and Communications Engineering
2007 — 2011
Skills
- Lvs
- Synopsys Icc
- Static Timing Analysis
- Timing
- Tcl
- Physical Verification
- Verilog
- Very-Large-Scale Integration (Vlsi)
- Icc2
- Electronics
- Awk
- Physical Design
- Synopsys Primetime
- Cmos
- Vlsi
- Linux
- Design Rule Checking (Drc)
- Primetime
- Timing Closure
- Sed
- Asic
- Drc
- Dft
- Floorplanning
- Clock Tree Synthesis
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