Anurag Upadhyay
Design Verification Engineer @Wipro
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WORK HISTORY
Design Verification Engineer @Wipro
Bengaluru, IN
Currently I\'m working as a Design Verification Engineer
EDUCATION
Dr APJ Abdul kalam Technical University Uttar Pradesh
B.tech
National Institute of Technology Agartala
M.tech
ABOUT ANURAG UPADHYAY
Currently Working as Design Verification Engineer at Wipro.Working on GLS,PAGLS, Debugging race condition,metastability. Worked on a SOC verification project.worked on Code & functional coverage.Debugging skills on verdi & writing new tests cases,Running regression with coverage.Enablement of tracker, checker, scoreboard.Good Understanding of Verilog, System Verilog and UVM methodology.Having experience on different protocols like I3C, AHB, UART,AXI.Good Understanding of of Testbench Architecture and its environment.Understanding of architecture of client GPU & it\'s flow how one die is connected to the otherD2D level Connectivity.Data flow from core to other I/O die & memory die.Knowledge of Assertion, Coverage.
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