Anurag Tiwari

WORK HISTORY

EDUCATION

ABOUT ANURAG TIWARI

Developed AMS Verification (Mixed Signal Verification) flow setup using Cadence and Synopsys tools. • Analyzing specification and creating simulation plan as a part of verification planning. • Creating and Validating Analog Behavioral Models vs Schematic. • Digital and Analog Mixed Signal Test Case creation, regression run and debug as per test case requirement. • Writing Auto-checkers for AMS (Verification) • Familiarized with System Verilog – UVM Testbench hierarchy and worked on regression and coverages. • Based on simulation plan detailed test-scenarios are set up using System Verilog to cover all the functionalities and reported the bug to the Digital/Analog Design Team. • Block Level understanding of analog blocks like Inverter, Buffer, Level Shifter, LDO, PLL, Transmitter, Receiver, DLL and Phase Aligner. • Experience in creating Synopsys Verilog-AMS-SPICE flow. • Worked with Cadence Virtuoso, AMS Simulator, ADE-L. • Worked with Synopsys VCS_XA, Customsim, Verdi, DVE and Waveview. • Generating random and constrained stimulus in a module-based test bench. • Generating stimulus model, creating various UVC (Universal Verification Component), Creating Test Cases. • Worked in preparing results documentation, presentation and excel. • Experience in working with technical teams at different time-zones and coordinating with groups at multiple locations.