Anurag Bagewadi
DFT engineer @Google --> ATPG | SCAN | IJTAG | DFT-RTL | DFT-DV
- Role
- Dft Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Anurag Bagewadi
As a Senior Design Engineer at NXP Semiconductors, I have the privilege to take DFT ownership of AI processing subsystems that specialize in neural network processing for training ML models. I handle many different responsibilities ranging from ATPG, SCAN INSERTION, DFT-RTL integration and design verification of many IPs like MBIST, IJTAG, Clocking and Boundary Scan. I have been appreciated, encouraged and entrusted with many important responsibilities across many projects ranging from Automotive to edge processing SOCs.I have a Master of Technology in VLSI Design and Embedded Systems from R. V. College of Engineering, Bangalore, where I developed my skills and knowledge in RTL Development, Scan Insertion, Field-Programmable Gate Arrays (FPGA) and other aspects of VLSI design. I also have valuable experience as a Silicon Design Engineer and a co-op engineer at AMD, where I led a small team in a Server SOC product and worked on Pattern Delivery of various IPs across SoC architecture. I am passionate about DFT and its applications in AI and ML, and I aim to contribute to the innovation and excellence of NXP and its products.
Experience
Dft Engineer
Jan 2024 — Present · Bengaluru, IN
Education
VDRIT
bachelors of technology, Electronics and Communications Engineering
2013 — 2017
RV College Of Engineering
Master of Technology - MTech, VLSI Design and Embedded Systems
2017 — 2019
Skills
- C
- Microsoft Office
- Microsoft Excel
- Matlab
- Javascript
- Kiel
- Arduino
- Powerpoint
- Microsoft Word
- English
- Teamwork
- Engineering
- 8051 Microcontroller
- Intel 8085
- Leadership
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