Anuradha Raghunathan

About Anuradha Raghunathan

Result oriented technical manager/leader with 20+ years of experience in all aspects of ASIC design flow including architecture, micro-architecture, logic design using RTL and firmware, synthesis, timing closure and post-si debug and correlation. Proven experience in breaking down complex problems into achievable tasks and delivering results with high quality on tight schedules. Created a high performing power validation team from scratch. Proactive and resolute program manager with extensive experience in driving closure of open issues involving cross-functional engineering teams by diligently following up and creating clear path of communication and improving efficiency along the way by putting processes, checks and detailed documentation in place. Competent expert in power estimation, pre-silicon power optimization, pre to post silicon power correlation and power management techniques in SoCs/CPUs including active and idle power management of CPU cores and Graphics. Reviewer for power validation papers for Intel’s Internal Conference.

Experience

1. Soc Power Lead

   Google

   Oct 2021 — Present · San Francisco, CA, US

   Power Convergence Lead for the 3+ Tensor SoCs that go into Pixel phonesDeveloped and drove the adoption of RTL power analysis across the org, starting from the evaluation of different tools, developing scripts and flows, setting targets on different metrics at the RTL level. Set power targets and metric targets for IPs and subsystems for different activity vectors and track and audit to achieve those targets. Guide the team on defining activity vectors that will be useful for power analysis and modeling. Drive cross functional efforts for power reduction by working with architecture, design, PD, DV and technology teams. Identify power inefficiencies at the SoC level by mining and analyzing data from previous projects and milestones using Python Streamlined the expectations from different stakeholders like DV, PD, Design with respect to power related deliverables. Serve as a technical expert in power to make go/no-go decisions on various optimizations based on trade off analysis.

Education

• University of Florida

  Masters, Electrical Engineering

  2003 — 2005

• Madurai Kamaraj University

  BE, Electronics and Communication

  1999 — 2003

Skills

• Semiconductors
• Spyglasslp
• Rtl Design
• Power Management
• Asic
• Intel
• Debugging
• Computer Architecture
• Application-Specific Integrated Circuits (Asic)
• Systemverilog
• Verilog
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Upf
• Low-Power Design
• Vlsi
• System on a Chip (Soc)
• Microarchitecture
• Circuit Design
• Firmware
• Logic Design
• Soc
• Low Power Design
• Processors