Anuraag Marepally
Senior Physical Design Engineer @NVIDIA
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WORK HISTORY
Senior Physical Design Engineer @NVIDIA
Hyderabad, IN
EDUCATION
Jawaharlal Nehru Technological University
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
Jawaharlal Nehru Technological University
Master of Technology (M.Tech.), vlsi-system design
SKILLS
ABOUT ANURAAG MAREPALLY
10+ years of experience in ASIC Physical Design field.Hands-on experience in complete backend flow - Logical Synthesis, Physical Synthesis, Floor Planning, Power Planning, Place & Route, Clock Tree Synthesis, SI Analysis, Signoff Timing Analysis and Timing Closure, Physical Verification and PERC, IR drop analysis and LEC.Strong fundamentals in Physical Design, ASIC flow, STA, EMIR and PV by way of handling distinct blocks in multiple projects.Worked on TSMC 3nm, 5nm, 7nm, 12nm, 16nm, 90nm, Samsung 14nm and GF 14nm technology nodes from RTL to GDS-II tape-out.Excellent hands-on over Cadence and Synopsys EDA tools.Good understanding in basics of digital design, cmos design and semiconductor devices
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