Anup Ramesh

Principal Engineer at Marvell Technology

Role
Principal Engineer at Marvell Technology
Location
San Francisco, CA, US
LinkedIn followers
500 followers

Experience

  1. Principal Engineer

    Marvell Technology

    Jun 2021 — Present · San Francisco, CA, US

Education

  • Visvesvaraya Technological University

    BE, Electronics and Communication

    2006 — 2010

  • North Carolina State University

    Master's degree, Computer Engineering

    2010 — 2012

Skills

  • Perl
  • Debugging
  • C
  • Verifica
  • Assembly Language
  • Xilinx
  • Systemverilog
  • Microprocessors
  • Modelsim
  • Vlsi
  • C++
  • Arm
  • Logic Design
  • Processors
  • Arm Architecture
  • Oop
  • Systemc
  • Application-Specific Integrated Circuits (Asic)
  • Amba Ahb
  • Algorithms
  • Problem Solving
  • Computer
  • Rtl Design
  • Tlm
  • Soc
  • Computer Architecture
  • Fpga
  • Asic
  • System Verilog
  • Verilog
  • Vhdl

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Anup Ramesh — Principal Engineer at Marvell Technology in San Francisco, CA, US | Unifers