Anup Mane
Physical Design Lead @ Intel Corporation | Synthesis, Low Power Design, PNR, Timing, Signoff | Formal Verification
- Role
- Physical Design Lead at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Anup Mane
I am a Senior VLSI Physical Design Lead with 17+ years of experience in ASIC/Structural…
Experience
Physical Design Lead
Dec 2018 — Present
Led the execution of multiple DDR partitions with a focus on high-quality design through Correct by Construction Approach. This included working with stakeholders from different domains across multiple geographical sites and collaborating for constraint definition & refinement, UPF feedbacks, Analog Custom Routing to meet stringent Timing Specs, CTMesh/Hybrid CTmesh, Floor-planning, Congestion Analysis, Timing Analysis, Caliber, Layout Verification & fixes to Final Closure with Quality and was a key Team player to provide necessary guidance to peers.Took ownership as the BA Site Lead for LEC/FEV Low Power Methodology, providing critical support for various IPs.
Skills
- Spice
- Pspice
- Formal Verification
- Circuit Design
- Debugging
- Vlsi Design
- Asic
- Modelsim
- Simulations
- Analog Circuit Design
- Logic Design
- Xilinx
- Eda
- Cmos
- Vlsi
- Low-Power Design
- Low Power Design
- Simulation
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