Anuhya Nagireddy

About Anuhya Nagireddy

I am 9+years experienced professional working at Intel Skill set:*Design Tools: Synopsys VCS, DC Compiler, Synopsys PrimeTime, Spyglass Lint, Spyglass CDC, Spyglass RDC, Ansys Totem, Cadence Virtuoso, Cadence Conformal ECO,MATLAB, VCLP*Hardware Description Language: Verilog HDL, System Verilog, Verilog-A*Scripting/Programming Languages: Python, C, TCL*Bus Protocols: SPI, UART, I2C, APB, AHB, PCIe(Intermediate)*Proficiency in • RTL Design using Verilog & SystemVerilog • RTL Simulation Synthesis and gate-level netlist generation • Static Timing Analysis (STA) • System Verilog Assertion-Based Constrained Random Verification • Signal Integrity concepts - High Speed Serial Interface (HSSI) • Design of SERDES, Decision Feedback Equalizers(DFE), Phase Locked Loop(PLL), Clock and Data Recovery(CDR) at System Level

Experience

1. Soc Design Engineer

   Intel

   Feb 2017 — Present

   Innovator in Tile Integration team that delivers Transceiver SoCs for Intel Agilex FPGA• Documented the microarchitecture document from the High-level Architecture specification and drove the IP design implementation, quality through DRC -Lint, CDC, RDC checks and implementedlow power methodologies• Consistently collaborated with the Verification and Physical Design team for feedback regarding the design intent• Led to early closure of verification efforts by analyzing waveforms and coverage reports• Provided timing constraints and analyzed timing reports for false paths. Reduced the physical design turnaround by 3 weeks by implementing manual ECO fixes• Increased the quality through automating DRC checks using a daily CRON Job for the team• Performed the EM/IR Analysis using Ansys Totem for custom IPs & provided critical feedback to layout engineers, reducing the PI issuesExtra-Curricular-• Site leader for an Employee Resource Group, with caters for the career development ofemerging professionals

Education

• Jawaharlal Nehru Technological University

  Bachelor of Technology (BTech), Electronics and Communications Engineering

  2010 — 2014

• Bharatiya Vidya Bhavans Public School

  High School

  1998 — 2008

• San José State University

  Master's degree, Electrical and Electronics Engineering

  2014 — 2016

Skills

• Cadence Spectre
• Perl
• Semiconductors
• Integrated Circuit Design
• Linux
• Logic Design
• C
• Html
• Rtl Design
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Synopsys Tools
• Simulink
• Unix
• Cadence Virtuoso
• Matlab
• Microsoft Excel
• Application-Specific Integrated Circuits (Asic)
• Computer Architecture
• Verilog
• Microsoft Office
• Vlsi
• C++
• Nc-Verilog
• Simulations
• Python
• Synopsys Primetime
• Xilinx Ise
• Logic Synthesis
• Cmos
• System Verification
• Asic
• Systemverilog
• Signal Integrity
• Analog Circuit Design