Anu Pranesh
Sr Asic Fpga Verification Engineer @Palo Alto Networks
San Jose, CA, US
EMAILS
a•••••••@paloaltonetworks.com
MOBILE NUMBERS
+12•••••••72
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WORK HISTORY
Apr 2021 — Present
Sr Asic Fpga Verification Engineer @Palo Alto Networks
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EDUCATION
2015 — 2017
University of Southern California
Master’s Degree, Electrical Engineering
2011 — 2015
Global Academy Of Technology
Bachelor’s Degree, Electrical and Electronics Engineering
SKILLS
Microsoft ExcelUniversal Verification Methodology (Uvm)PowerpointLinuxMicrosoft WordC++LeadershipAltera QuartusResearchPythonCCadence VirtuosoMicrosoft PowerpointPresentationsVerilogSystemverilogVery-Large-Scale Integration (Vlsi)MatlabTeamworkJavaPerlApplication-Specific Integrated Circuits (Asic)Microsoft Office
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