Anthony Polomik

About Anthony Polomik

Physical Design & CAD work in a primarily Cadence & Synopsys environment.Specialties: Synopsys ICC2, Mentor Calibre, Cadence Virtuoso/VXL toolset, Cadence Place & Route tools (SoC Encounter, Wroute, Nanoroute).Cadence Skill language, ICC tcl, Mentor Calibre SVRF/TVF, perl, shellSoC/Core/macro level floorplanning and methodologyPower meshing, voltage islands, MCMM, padring methodology, submicron design.Design automation, P&R methodologyPhysical Synthesis & Static Timing AnalysisSoftware developmentDC, Milkyway, libgen (NDMs), StarRC, PrimeTime.

Experience

1. Senior Physical Design Engineer

   Microsoft

   Aug 2018 — Present

Education

• Florida Institute of Technology

  MS

  1996 — 1999

• Florida Institute of Technology

  BS

  1991 — 1996

Skills

• Icc
• Primetime
• Drc
• Floorplanning
• Csh
• Sed
• Asic
• Cadence Virtuoso
• Semiconductors
• Tcl
• Dc
• Timing Closure
• Debugging
• Soc
• Unix Shell Scripting
• Processors
• Cmos
• Scripting
• Software Development
• Perl
• Eda
• Static Timing Analysis
• Synopsys Tools
• Rtl Design
• Shell Scripting
• Unix
• Integrated Circuit Design
• Microprocessors
• Verilog
• Low-Power Design
• Algorithms
• Physical Design
• Linux
• Place & Route
• Lvs
• Cadence
• C
• Signal Integrity