Antardipan Pal

About Antardipan Pal

An enthusiastic and energetic individual with a keen interest in new innovative technology. I am a diligent worker who enjoys collaborative work to develop new skills and solve new challenges. More than 5 years of experience in design and optimization using various EDA tools. More than 3 years of experience in Nano device design, optimization and modelling using Synopsys TCAD and optical design and optimization using Synopsys Optical Design Suite. One year experience in funded project in Analog, Mixed Signal and RF IC design using Cadence Design tools. Proficient in using various EDA and CAD Tools for device design, modelling and circuit design simulation and optimization. Currently I am a Device Modeling Engineer under the Advanced Technology Development group at Texas Instruments. Expertise in developing physics-based semiconductor device models (nominal, statistical, corner, mismatch models, etc.) for various types of devices (MOSFETs, diodes, NVMs, etc.) for different TI technologies and products.Previously I worked as a Device Modeling Engineer in the 3D NAND NVM group at Intel Corp. where I worked with Intel\'s 170s Technology for modeling devices for the NAND array. Also got hands on experience with device characterization using the Cascade 300 probing station. I graduated with a P.hD. in Electrical Engineering from the Electrical & Computer Engineering Department at UNC Charlotte. My doctoral research revolves around the design of a MSM optoelectronic device called the Light Effect Transistor (LET) and using the same to design a novel Electronic-Photonic 6T Hybrid SRAM. The LET is a nano-wire based gate-less Opto-Electronic device structure which can emulate the I-V characteristics of FETs. The LETs provide much better performance in terms of speed and power consumption (gate related parasitic, SCEs are not present, the body leakage is almost 10 orders of magnitude lesser as compared to FETs, thanks to the simplistic structure of the LET), and a single LET can perform more functions like optical logic operations, amplifications etc. that cannot be performed by a single FET. Proposed a novel hybrid FET/LET 6T SRAM replacing the access FETs with LETs and the electrical word lines with optical waveguides. Also, a novel 3D stacking approach has been proposed to improve illumination efficiency and compactness of the hybrid structure, where LETs from 2 adjacent 6T cells are grouped which reduces the number of OWG openings by a factor of 4!

Experience

1. Senior Engineer (Technology Development) Device and Process Tcad

   Micron Technology

   Mar 2025 — Present · Hyderabad, IN

   Involved in developing CMOS device for future NAND technology nodes.Optimization of device performance (process and device level optimization) for low and high voltage NAND devices.Worked on device reliability analysis for low voltage NAND devices.

Education

• Jadavpur University, Kolkata

  Master of Technology - MTech

• University of North Carolina at Charlotte

  Doctor of Philosophy - PhD

  2017 — 2022

• St.Thomas' Collge of Engineering & technology

  Bachelor of Technology (B.Tech.)

Skills

• C
• Programming
• Microprocessor, Assembly Language Programming , Microcontroller , Networking
• Windows
• Sql
• C , C++ , Matlab , Vhdl , Pspice ,Avr
• Gsm
• Java
• C++
• Microsoft Excel
• Matlab