Ansuman Rout

About Ansuman Rout

I am a passionate and skilled Semiconductor Engineer with a proven track record in 2 Live Projects in Firmware and Emulation/Pre-Si Verification Domains.=> Currently working with a Leading Product Based Company as CW in Product Validation & Firmware Validation Team.=> Have Extensive experience in Test Case Planning and Test Case Development for a Next Generation Data Center & Server Based Processor covering both Pre-Si and Firmware Features in Sub Domains like Boot/Reset, Power Management, Unified Patching, Interconnect Peripherals (PCIe, CXL), Fuses etc.=> Have hands on Experience in Full System Simulation tools like Simics and Frameworks like Python-System Verilog. I also have experience in Github and flow tools like Jira.=> Been through 1 Live Project in My Current Job and was involved in TR Phase of another project with being part of the team working on Content Side at Intel during Internship.=> Had the Opportunity to Lead as a POC for Certain Sub-Domains => Have Exposure to Synopsys ZeBu Emulators, Synopsys Verdi Debug Tool, Python, Cadence Perspec System Verifier, Interconnect Protocols like PCIe till Gen 5 and CXL 2.0. Also gained working knowledge on SystemVerilog and UVM Methodology during the tenure of Internship.+>Holds a M. Tech. in VLSI Design from prestigious VIT University, Chennai, Tamil Nadu and a B. Tech. in Electrical Engineering from Siksha \'O\' Anusandhan University, Bhubaneswar, Odisha.

Experience

1. Semiconductor Product Validation Engineer

   UST

   Aug 2023 — Present · Bengaluru, IN

   Working in Test Creation Development Team, Responsible for Creating Test Cases, Test Plans & Scenarios to be used for Pre-Silicon & Firmware Verification by Client for a Next Generation Data Center & Server Based Processor-> Have Experience in Leading as a POC for a Team of 5 each working in different Sub-Domains-> Have Experience in Sub-Domains Like Boot/Reset, Power Management, Patching, Interconnects (PCIe/CXL) etc-> Have Experience in Full System Simulation & Building Automated Scripts of the Test Cases. Also have Worked on Python-System Verilog Framework-> Have Exposure in Simics, Python, Linux and Flows like GitHub, Jira etc.

Education

• D.A.V. Public School, CDA-6, Cuttack

  10

• Prabhujee English Medium School, Sambalpur

  12th

• Vellore Institute of Technology

  Master of Technology - MTech

  2021 — 2023

• Institute of Technical Research and Education,SOA University,Bhubaneswar,Odisha

  Bachelor in Tech

  2016 — 2020