Anson Jose
Training - Advanced Physical Design and Verification @Maven Silicon
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WORK HISTORY
Training - Advanced Physical Design and Verification @Maven Silicon
Currently enrolled in an Advanced Physical Design & Verification training course, focusing on the RTL-to-GDSII flow, including floorplanning, placement, CTS, routing, and sign-off using industry-standard EDA tools like Synopsys and Siemens EDA
EDUCATION
Georgian Academy English Medium High School, Thiruvankulam
Secondary school education
St Peters HSS Kolenchery
Higher secondary education, Computer Science
Hamburg University of Technology
Master of Science - MS, Microelectronics and Microsystems
Mar Athanasius College of Engineerng (MACE)
Bachelor of Technology, Electrical, Electronics and Communications Engineering
ABOUT ANSON JOSE
Passionate about VLSI Physical Design Engineering I\'m a Master’s student in Microelectronics and Microsystems at TUHH, currently working as a Physical Design Intern at Dream Chip Technologies GmbH in Hannover. My work focuses on analysing physical design flows for the GF22FDX technology node using Cadence Innovus, porting netlists to GDSII, converting legacy scripts to Stylus Common UI with TCL, and performing PPA analysis to optimise design flows. Alongside, I\'m enrolled in an Advanced Physical Design & Verification course, gaining hands-on expertise in the RTL-to-GDSII flow (floorplanning, placement, CTS, routing, and sign-off) using Synopsys and Siemens EDA tools. Skilled in VLSI, Physical Design, TCL scripting, Verilog, and digital implementation. I aim to contribute to innovative semiconductor design and physical implementation challenges
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