Anshul Goel
Engineering Manager at Google Silicon
- Role
- Engineering Manager at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Anshul Goel
19+ Years of experience in ASIC Front end verification, post silicon bring-up/validation, Micro-Architecture review, System Architecture review, RTL design, analyzing SW requirements and debugging on SW environment- Manager/Lead Pixel SoC DV team for all Compute (CPU, GPU, DSP & TPU) and IOs subsystems(UFS, PCIE, USB and low speed). w/ first time right vision- Manager / Verification lead for Multiple IPs - AI accelerator, Multicore(64,128.) L1$+ distributed L2$ coherency IP, SPT IP, MIPI CSI2/DSI, I3C - Lead fullchip verification team for three projects in Cisco Systems(N7K product line). Experience in handing multi geographic team, complete environment (single environment used for fullchip simulation, dft, gate sim, cpu access(pci-e) and SerDes verification), regression closer and schedule- Expert in setting up highly productive and result oriented teams that can delivery ASIC/IP\'s with first time right mind set. Managed contractual teams remotely and in-house- Good experience in selection of verification strategy and methodology considering trade-offs for fullchip/module level verification, with risk, quality and schedule in perspective- Domain Expertise - Setup verification strategy(UVM, C based, Formal) for Multi-core(64,128,256) L1 $+ distributed L2$ coherency IP- 10yrs of experience in Semiconductor Networking domain - MacSec, Schedules/Rate limiters/QoS/Data Path, Pause - CBFC and Std, Ethernet, EPON, SPI3/4.2 - Presently working in Automotive Semiconductor Industry(Jan/2017)- Radar Signal Processing toolkit IP - MIPI for Radar and vision products.(first time industry solution)- Ethernet, Gateways for Automotive- Low speed peripherals - I2C/I3C IP- Vision - Feature preparation engine -(scalar, luv, hog).
Experience
Engineering Manager
Dec 2022 — Present · IN
Manager/Lead Pixel SoC DV team for all Compute (CPU, GPU, DSP & TPU) and IOs subsystems(UFS, PCIE, USB and low speed)- Cross-domain/Chip lead for DSP subsystem, including Arch, DE, DV, PD, DFT & SW.
Education
Manipal Academy of Higher Education
MS, VLSI-CAD
Skills
- Systemverilog
- Functional Verification
- Fpga
- Asic
- Debugging
- Testing
- Application-Specific Integrated Circuits (Asic)
- Vlsi
- Verilog
- Vmm
- Ncsim
- Rtl Design
- Soc
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