Anoop Kiran

About Anoop Kiran

Anoop Kiran currently, is a Senior Digital Design Verification Engineer at Nvidia with over 9 years of experience. Previously, as an Application Engineer at Synopsys, he specialized in VCS/Verdi advanced debug and ML-based coverage optimization. At AMD, he received a \"Spotlight Award\" for technical leadership in DDR5 protocols and excelled in mixed-signal verification for high-speed SerDes. Currently, at Nvidia, Anoop developed UVM-based methodologies that accelerated SerDes verification efforts from days to hours. Over the last three years, he identified four critical EDA tool bugs during his verification work. Technology:DDR5 PHY, DFI protocol. DRAM protocol, SerDes RX.SystemVerilog Design/Debug/Verification.Tools:VCS, Verdi, DVE, Synopsys Design Compiler. QuestaSim.

Experience

1. Sr Design Verification Engineer - Serdes

   NVIDIA

   Jan 2025 — Present · Santa Clara, CA, US

   Verified DSP blocks in the Receiver side of SerDes designs. Developed multi-cycle accurate UVM reference models for DSP blocks featuring feedback loop, saturation, scaling, and filtering logic- Verified Jitter Canceling block by injecting sinusoidal jitter and confirming effective cancellation- Developed a methodology to accelerate UVM component development & debug using AI agents; reducing time from days to hours. Found 2 Verdi bugs and reported to Synopsys. Later fixes were used as part of the flow.Design Knowledge Gained- PAM4, Partial Response, Multi-Level adaptation of signals, Jitter Correction by resampling (delta V), Interference Correction- Sgnal Integrity: Linear vs Non Linear, Offset (to adjust baseline).

Education

• Portland State University

  Master's degree

• Siddaganga Institute Of Technology

  Bachelor's degree at Siddaganga Institute of Technology (SIT)

Skills

• Python
• Transistor Technology
• Cmos Design/Debug
• Cadence Virtuoso
• Ldo Regulator
• Ltspice
• Cmos Scaling to Timing Enhancement
• Verilog
• Linux
• Dynamic Timing Improvement
• Digital Vlsi Basics
• Power,Area,Timing Co-Relation
• Microsoft Office
• System Verilog
• Cadence
• Digital Vlsi Basics
• Finfet
• Matlab
• Dynamic Timing Analysis and Improvement
• Verifica
• Research
• Cmos
• Analog Vlsi Basics
• Tcl
• C
• Systemver
• Dc Compiler
• Transistor Technology
• Vhdl
• Wireless
• Ic Compiler
• Sta
• C++
• Universal Verification Methodology (Uvm)
• Ldo Regulator
• Hspice
• Bandgap References
• Rtl Design
• Verification and Validation (V&V)
• Semiconductor Process