Anoob Eapen C.

About Anoob Eapen C.

I am a Senior Technical Engineer with a comprehensive 12-year background in the semiconductor industry, specializing in Physical Design and CAD (8 years) and Circuit Design (4 years). My current focus is at the absolute forefront of the industry: the integration of AI/ML-driven EDA tools to achieve superior PPA and accelerated design closure.Key Technical Expertise:* Advanced Nodes: Proven expertise on the industry\'s most cutting-edge process nodes, including 18A, 2nm, 3nm, 5nm, 7nm, and 28nm.* AI/ML in EDA: Specialized in the deployment and operational enhancement of machine learning solutions, including Synopsys DSO.ai and Cadence Cerebrus, to automate design space exploration and optimize project timelines.* PPA & Timing Closure: Expert in driving block-level timing and power closure by leveraging ML-driven insights to resolve complex P&R bottlenecks and intricate design constraints.* Full ASIC Flow: Hands-on mastery of the entire Physical Design flow—Floor Planning, Power Planning, Placement, CTS, P&R, Timing Analysis, and ECOs—utilizing both Synopsys ICC/ICC2 and Cadence Innovus.Leadership & Innovation:As a proactive leader and collaborative team player, I combine deep analytical thinking with an innovative approach to tool deployment. I am dedicated to streamlining complex workflows and mentoring cross-functional teams to meet the rigorous demands of next-generation, high-performance silicon projects.

Experience

1. Soc Design Engineer

   Intel

   Feb 2023 — Present · Bengaluru, IN

Education

• Kendriya Vidyalaya kottayam

  Schooling, Bio-maths

  1996 — 2007

• Saintgits College

  Engineer's Degree, Elctronics and Communication

  2007 — 2011

• KARUNYA UNIVERSITY

  Master's Degree, VLSI Design

  2012 — 2014