Annapoorna Hm

About Annapoorna Hm

As a passionate and dedicated Design Verification Engineer, I specialize in ensuring the highest quality and reliability of complex digital designs. My expertise lies in developing and implementing verification environments, using industry-standard methodologies such as UVM.Through my career, I have successfully contributed in IP Verification of two high-profile projects at AMD, collaborating with cross-functional teams to deliver solutions. My proficiency in PCIe, SPI, UART, AXI has enabled me to tackle verification tasks and achieve results- Proficient in Verilog, System Verilog, UVM and TCL scripting- Protocols known: PCIe, AXI, APB, SPI, UART- Experience in creating and executing comprehensive test plans, testbenches, and verification IPs- Strong analytical and problem-solving skills, with a keen eye for detail and a commitment to excellence- Excellent communication and teamwork abilities.I am always eager to learn and stay updated with the latest industry trends and technologies. My goal is to continue growing as a Design Verification Engineer, contributing to innovative projects and making a meaningful impact in the semiconductor industry. I enjoy applying my skills and knowledge to solve challenging problems and deliver quality results.

Experience

1. Design & Verification Engineer

   AMD

   Jul 2023 — Present · Hyderabad, IN

   Worked on projects Telluride and Apex.Apex project involves verification of Logic Core Apex IP in Vivado Application. Roles & Responsibilities: Worked on Understanding Apex and it’s blocks features. Worked on understanding VIP support and integration. Worked on integrating Synopsys VIP with Vivado Ip wrapper for basic and functional testcases. Verified register configurations and GUI parameters according to the usecases/scenarios. Verified SPI and PCIe functional path.Worked on Multimedia deployment related project which is Telluride. Major block worked on in this subsystem is PCIe. I was involved in IP verification of PCIe.Roles & Responsibilities: Understanding the MMI and PCIe block features. To create design in Vivado for GPU and PCIe blocks. Verifying the GUI parameters with the register configurations (CDOs) according to the usecases/scenarios. Automated the GUI checks for every build. Worked on functional verification in IP for PCIe block. Worked on understanding the environment and providing the configurations to Validation team for failing cases. Worked on Regression. Observing waveform generated with expected output. Debugging on the error generated and reporting the same

Education

• Sri Venkateshwara College of Engineering, BANGALORE

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering

• Portland State University

  Master's degree, Electrical, Electronics and Communications Engineering