Anmol Handa
Advance VLSI Design and Verification Trainee
- Role
- Advanced Vlsi Design and Verification at Maven Silicon
- Location
- Kanpur, IN
- LinkedIn followers
- 500 followers
About Anmol Handa
I am an aspiring and self-driven engineer who is conversant with a wide range of technologies. However, I have a great ambition to break into and build a name in the VLSI Industry
Experience
Advanced Vlsi Design and Verification
Apr 2022 — Present · Bengaluru, IN
RTL Coding with Verilog Synthesizable Constructs. Designs FSM-based systems and tests them using simulation. • SystemVerilog and the Universal Verification Methodology(UVM) were used to design the test bench infrastructure. • Methodologies for verification include constraint random coverage-driven verification and Assertion Based Verification with SystemVerilog Assertions. • Surface-level knowledge of CMOS Fundamentals, Code Coverage, Functional Coverage, and Static Timing Analysis.
Education
PSIT Kanpur (Pranveer Singh Institute of Technology)
Bachelor of Technology - B.Tech
2015 — 2020
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.