Ankur Jaiswal

About Ankur Jaiswal

Analog Mixed Signal system engineer with strong understanding of design and verification methodologies with 6+ years of experience in analog mixed signal IC design development in process though 28nm, and verification of complex analog and digital systems. My skills and experience include but are not limited to-Define testbench infrastructure using SystemVerilog and developed scripts, methodologies and tools for efficiency and quality improvements-Responsible for complete chip level verification of mixed signal IC including test plan, stimulus implementation, gate level simulation-Development of System Verilog tests for verification in UVM based flow and verification IP following OOPs concepts for constrained random and metric driven verification-Verification of Mixed-Signal designs with a mixture of digital (RTL or netlist) and analog blocks (models or schematic)-Behavioural modelling of analog functions in Systemverilog/Verilog-AMSEDA Tools: Cadence Xcelium, vManager, Virtuoso ADE Verifier, Spectre X/APS/FX, SimVisionDesign and Modelling Language: System Verilog, Verilog-AMS, Veriog-A, MATLABScripting Language: Python, Perl, UNIX Shell scripting

Experience

1. Ams Verification Lead

   Texas Instruments

   Nov 2024 — Present · Bengaluru, IN

Education

• Nanyang Technological University Singapore

  Master of Science (MSc), Integrated Circuit Design

  2014 — 2016

• Birla Institute of Technology, Mesra

  Bachelor of Technology (B.Tech.), Electronics and Communication Engineering

  2010 — 2014

• Army Public School, Jhansi

  Student

  2005 — 2009

• Technical University of Munich

  Master of Science (MSc), Integrated Circuit Design

  2014 — 2016

Skills

• C
• Opnet
• Mixed-Signal Ic Design
• Cadence Virtuoso
• Robotics
• Sensors
• Matlab
• Xilinx Ise
• Python
• Integrated Circuit Design
• Intel 8051
• Data Structures
• Analog Circuit Design
• Embedded Systems
• Arduino
• Digital Electronics
• Synopsys Tools
• Orcad Capture Cis
• C++