Ankur Yadav

About Ankur Yadav

Professional Experience: Domain : FPGA Design/PrototypingRTL design: VHDL, Verilog,HVL: VerilogProtocol: Good understanding of the PCIe 2.0, low-speed peripherals like UART/I2C/SPI and AMBA(AXI/APB)Topics- Synthesis, STA(timing closure), Place and route, RTL Coding, FPGA architecture.Debugging-Strong troubleshooting, analytical and Debugging experience in multi FPGA hardware board issues using lab equipment such as oscilloscopes, logic analyzer, protocol analyzer (Lecroy). Software Skills- C, PythonTools- Xilinx design suites 14.7,Vivado2014.3, ModelSim(10.1a), Cadence (IES) simulator (11.1), Synopsys Synplify Pro 2013.03Debug tool: lauterbach and Xt-gdb

Experience

1. Smts

   AMD

   Jun 2025 — Present · Hyderabad, IN

Education

• CDAC

  PG Diploma, vlsi

  2011 — 2012

• Rajiv Gandhi Prodyogiki Vishwavidyalaya

  Bachelor’s Degree, Electronic and Communications Engineering

  2007 — 2011

Skills

• Vhdl
• High Level Synthesis
• Trace32
• P&R
• Verilog
• Integrated Circuit Design
• Chipscope Pro
• Xst
• Cmos
• Synplify
• Rtl Verification
• Planahead
• Application-Specific Integrated Circuits (Asic)
• Lauterbach
• Xilinx
• Emulation
• Xilinx Ise
• Digital Electronics
• Rtl Design
• Modelsim
• Place & Route
• Synplify Pro
• Hdl Designer
• Field-Programmable Gate Arrays (Fpga)
• Chipscope
• Digital Design
• Gate Level Simulation
• Timing Closure
• Fpga
• Asic
• Rtl Coding
• Fpga Prototyping
• C
• Vlsi