Ankur Vaish

About Ankur Vaish

15+ years of Design verification experience with experience on architecting and developing constrained random coverage driven UVM based testbenches from scratch.Expertise in PCIe Protocol - Gen 1 to Gen 6Experience in Building/Managing/Leading Verification Teams.Experience on all level of Verification that includes IP Level Verification, Subsystem Level Verification and SoC level Verification.Experience in writing VIPs for Simulation as well as Emulation.Experience with UVM, Verilog/System Verilog, Synopsys/Mentor/Cadence tool sets.Experience on Leading multi-team and multi-site working environment.

Experience

1. Design Verification Manager, Security

   Google

   Sep 2023 — Present · Bengaluru, IN

   Leading/Managing the BLR Pixel/gChips Security DV Team.

Education

• Indian Institute Of Information Technology Allahabad

  B.Tech, Electronics and Communication

  2006 — 2010

• Dewan Public School

  Intermediate, Science

  2004 — 2006

Skills

• Tcl
• Veritas Cluster Server
• C++
• Device Drivers
• Arm
• Vcs
• Static Timing Analysis
• Uvm
• Functional Verification
• Systemc
• Debugging
• Rtl Design
• C
• Programming
• Modelsim
• Embedded Systems
• Eda
• Simulation
• Soc
• Verilog
• Integrated Circuit Design
• Computer Architecture
• Semiconductors
• Fpga
• Asic
• Ic
• Emulation
• Vlsi
• Digital Design
• Xilinx
• Systemverilog
• Vhdl
• Simulations
• Application-Specific Integrated Circuits (Asic)
• System Verilog