Ankit Gupta

About Ankit Gupta

Working on Timing Closure activities on multimillion gate SoC\'s on 10nm. Experience in - Full Chip Timing Closure- Constraint Validation and Clean Up- Development and Implementation of Synthesis Methodology- Development of STA Methodology- Development of full-chip timing constraints- Logic Equivalence Check- Definition of clock-tree strategy- Interaction with P&R teamSpecialties: STA, Timing Constraints Development,Synthesis.Tools Used:Synopsys - Design Compiler Prime Time Formality HSpiceCadence - RC Compiler ETS LECAtrenta - Spyglass

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Aug 2024 — Present · Bengaluru, IN

Education

• Delhi College of Engineering

  Master of Engineering, Electronics and Communication

  2009 — 2011

• Hemwati Nandan Bahuguna Garhwal University

  B.Tech, Electronics & Communication

  2005 — 2009

Skills

• Logic Synthesis
• Physical Design
• Vlsi
• Eda
• Timing Closure
• Synthesis
• Primetime
• Systemverilog
• Low-Power Design
• Spyglass
• Verilog
• Rtl Design
• Functional Verification
• Asic
• Soc
• System on a Chip (Soc)
• Static Timing Analysis
• Digital Electronics
• Synopsys Tools