Ankita Saxena
- Role
- Soc Validation Engineer at Intel
- Location
- Hudson, MA, US
- LinkedIn followers
- 500 followers
About Ankita Saxena
ASIC Verification Engineer with wide experience in System Verilog/ UVM methodologies…
Experience
Soc Validation Engineer
May 2018 — Present
Education
Delhi College of Engineering
Bachelor of Engineering, Electronics and Communication
2004 — 2008
Gotham Writers
Memoir writing, Mystery writing, Creative Writing
St. Francis de Sales
High School
1999 — 2004
Appalachian mountain club
Winter Hiking 101
North Carolina State University
M.S, Electrical Engineering
2010 — 2012
Skills
- Functional Verification
- Computer Architecture
- Verilog
- Modelsim
- C
- Java
- Algorithms
- Orcad
- Ofdm
- Wavelets
- Simulations
- Rf Design
- Digital Communication
- Asic
- Mimo
- Data Compression
- Information Theory
- Systemverilog
- Cdma
- Linux
- C++
- Matlab
- Debugging
- Digital Signal Processors
- Testing
- Dsp
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