Anjaneyulu Adepu

Senior Lead Engineer @高通

Hyderabad, TG, IN

EMAILS

[email protected]

MOBILE NUMBERS

+91 *********19

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WORK HISTORY

Jul 2024 — Present

Senior Lead Engineer @高通

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Hyderabad, IN

EDUCATION

2006 — 2010

Jawaharlal Nehru Technological University

Bachelor of Technology - BTech, in Electronics and Communications Engineering

2010 — 2012

Jawaharlal Nehru Technological University

Master of Technology - MTech, in VLSI System Design

SKILLS

Very-Large-Scale Integration (Vlsi)System on a Chip (Soc)SocArmApplication-Specific Integrated Circuits (Asic)Timing ClosureEmbedded SystemsEdaTclRoutingCadencePhysical DesignModelsimVhdlClock Tree SynthesisPerl ScriptingRtl DesignFloor PlanDigital Circuit DesignXilinxSystemverilogCompilersVlsiPlacementStatic Timing AnalysisEcoShell ScriptingArm ArchitectureVlsi Physical DesignCPowerplan

ABOUT ANJANEYULU ADEPU

Working on technology nodes ranging from 4nm,5nm,7nm,14nm and 28nm PnR.* Working on design complexity ranging from 500k to 2M multimillion instances Designs.* Experienced in block level & Subsystem Level implementation from Netlist to GDS-II which includes, Floor planning, Power plan, Placement, Cts, Routing, & STA, Extraction, DRC, LVS, Signoff.* Experienced Post-route timing closure with STA by using primetime* Worked on Industry Standard EDA Tools Innovus (Cadence), ICC & ICC2,Prime Time (Synopsys), Calibre(Mentor Graphics).* Scripting : Shell,Tcl perl.* HDL: Verilog.*OS: Linux (Ubuntu,Suse), Windows.

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