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Anita Fulvani

Analog Mixed Design Verification Engineer Cadence India - Ex INTEL

Role
Principal Design Engineer at Cadence
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
EngineeringView LinkedIn profile

Experience

  1. Principal Design Engineer

    Cadence

    Oct 2024 — Present · Bengaluru, IN

    Currently working on AMS verification for UCIe (Universal Chiplet Interconnect Express) to ensure seamless integration and reliable functionality of high-speed chiplet interconnects.

Education

  • Nirma University

    Master of Technology (M. Tech), VLSI

    2016 — 2018

  • Gujarat Technological University (GTU)

    Bachelor of Engineering (B.E.), Electronics and Communications Engineering

    2009 — 2013

Skills

  • Microsoft Office
  • Verilog
  • Ni Multisim
  • Microwind
  • Xilinx Project Navigator
  • Visual T-Cad
  • C
  • Keil Uvision
  • Teaching
  • T-Spice
  • Perl
  • Engineering

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Anita Fulvani — Principal Design Engineer at Cadence in Bengaluru, KA, IN | Unifers