Anirudha Rao
Post-Silicon Validation Engineer | UCIe • PCIe • Power Delivery • SerDes | Python Automation | 4+ Yrs @ Intel
- Role
- Post-silicon Validation Engineer Ucie, Pcie, Power, Serdes Python Intel Open to Global Roles at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Anirudha Rao
Post‑Silicon Validation Engineer at Intel with 4+ years of experience in first‑silicon…
Experience
Post-silicon Validation Engineer Ucie, Pcie, Power, Serdes Python Intel Open to Global Roles
Jul 2021 — Present · IN
Lead validation for Power delivery IP\'s— covering blocks like ADC, DAC, PWM, BGR, and LDO • Developed Python-based automation tools for lab instrumentation (oscilloscope, SMU, DMM), reducing data analysis time by 70% • Validated UCIe die-to-die interconnect under voltage, frequency, and temperature corners • Conducted SerDes PHY bring-up and validation across protocols: PCIe Gen3/Gen4, Ethernet, USB, CPRI, JESD • Executed internal and external loopback, link training, eye diagram margining, and regression analysis • Worked closely with RTL, firmware, DFX, and ATE teams to root-cause silicon issues and close them before volume ramp • Documented post-silicon issues in errata logs and presented debug summaries to senior engineering teams
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