Anirudh Kamath
Sr. CPU Post Silicon Verification Engineer @AMD
- Role
- Sr Cpu Post Silicon Verification Engineer at AMD
- Location
- Los Angeles, CA, US
- LinkedIn followers
- 500 followers
About Anirudh Kamath
Actively looking for Memory Design, Physical Design & CPU ASIC Design full time roles.I am a graduate student at the University of Southern California pursuing an M.S in Electrical Engineering specializing in Computer architecture and Digital VLSI design. I have taken courses on Computer System Organization, VLSI & Memory systems design, MOS VLSI circuit design & Integrated Memory and Devices Technologies.Framework : SRAM ( Design & Optimization), DRAM Design, Cache Coherency, Cache mapping techniques, CPU pipeline design, Tomasulo algorithm(IOI OOE IOC, IOI OOE OOC), Virtual memory.
Experience
Sr Cpu Post Silicon Verification Engineer
Jul 2025 — Present · Austin, TX, US
Education
University of Southern California
Master of Science - MS, Electrical and Computer Engineering
N M A M Institute of Technology, NITTE
Bachelor of Engineering, Electronics and Communications Engineering
Expert
Pre University, PCMB
Sharada Vidyalaya Kodialbail, Mangalore
10th Grade, Central Board of Secondary Education
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