Aniruddha Mukherjee
Layout Design Engineer
- Role
- Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Aniruddha Mukherjee
Domain Worked : Compiler Memory Layout, Analog LayoutTech Node Worked : FinFET-3nm GAA, 4nm,5nm, 11nm, 12nm, 14nm, 16nm, 17nm, 18nm FDSOI;CMOS-22nm, 28nm, 40nm, 55nm, 110nm, 180nmAnalog-90nm, 130nmFoundry worked on : Samsung, TSMC, GF, UMC, SMIC, Huali etc.Responsibility : Leaf cell to Instance Development, Verifications like DRC, LVS, DFM, LFD, EMIR etc.Tool used : Virtuoso L, XL for Layout; Calibre for DRC, LVS, DFM; Voltus FI, Totem for EMIRI like challenging environment and believe in Team work.
Experience
Staff Engineer
Apr 2025 — Present · Bengaluru, IN
Memory layout design
Education
RV-VLSI Design Center
Post Graduate Diploma in Advanced Studies in ASIC Design, VLSI Back-End Design
2014 — 2014
West Bengal University of Technology, Kolkata
Bachelor of Technology (BTech), Electronics and Communications Engineering
2007 — 2011
West Bengal University of Technology, Kolkata
Master of Technology (MTech), VLSI
2011 — 2013
Kanailal VidyaMandir
Madhyamik, Regular
1999 — 2005
Durgacharan Rakshit Banga Vidyalaya
Higher Secondary, Pure Science
2005 — 2007
Skills
- Tanner Eda
- Xilinx Ise
- Analog Circuit Design
- Cmos
- Calibre
- Linux
- Modelsim
- Digital Circuit Design
- Vlsi
- Static Timing Analysis
- Drc
- Lvs
- Very-Large-Scale Integration (Vlsi)
- Layout
- Perl
- Verilog
- Pspice
- C
- Vhdl
- Electronics
- Standard Cell
- Application-Specific Integrated Circuits (Asic)
- Memory Leaf Cells
- Asic
- Low Power Systems
- Perl Script
- Pyxis
- Matlab
- Ltspice
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