K A Kumar
Lead Design Engineer
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About K A Kumar
SKILLS- Strong Knowldge on UPF low power standard (UPF 1.0 & 2.0 & 2.1)- Strong Knowledge on Low Power techniques (Clock gating, Power gating, Muiti_Vt, DVFS, multi voltage)- Generation of UPF using UPF Gen & Debugging using the VCLP- Estimation of power by using the Power Artist (PA) Flow- Estimation of power by using the joules Flow - Estimation of power by using the Prime TIme (PTPX)- Estimation of power by using prime power RTL(PPRTL)- RTL Design (verilog & system verilog)- Lint & CDC & RDC (Spyglass)- Synthesis (Genus flow)- Protocols like I2C, SPI, UART,AMBA
Experience
Lead Design Engineer
May 2025 — Present
Education
Vignan's University
Master's degree, VLSI Design
JNTU Kakinada
Bachelor of Technology (B.Tech), Electronics and Communications Engineering
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.