Anil Vemulapalli
Senior Staff Engineer @Qualcomm
Signup · Get unlimited contacts
WORK HISTORY
Senior Staff Engineer @Qualcomm
San Francisco, CA, US
EDUCATION
Acharya Nagarjuna University
B.Tech, EEE
Indian Institute of Technology, Madras
M.Tech, Microelectronics and VLSI Design
ABOUT ANIL VEMULAPALLI
Semiconductor professional with 12+ years of experience in PDK (Process Design Kits) development, Physical Design Verification, CAD and Design methodology.Career Summary: PDK development for 7nm(finFet), 14nm(finFet), 20nm, 28nm, 45nm, 130nmPDK and Physical design verfication for 14nm,22FDX,20nm,28nm,45nm,65nm,90nm,130nm,180nm,250nm technologies. EDA Tool Expertise: Virtuoso, ADE, Spectre, Ultrasim, Assura, QRC, Voltus-FI, VPS, EAD, HSpice, Star-RCXT, Hercules, Astro, ICC, ICC2, Primetime, Calibre DRC/LVS/PERC/xRC/xACT/RVE, ELDO, IC station, Totem/Redhawk, Viso, Belledonne, BrennerSoftware Expertise: SKILL, Phthon, Perl, Ocean, Tcl, Shell, Linux, Perforce, Design Sync.Experience in QRC, StarRC LPE decks developmentExperience in Cadence techfiles, P-cells, symbols, Callbacks, CDFs developmentExperience in PEX QA flow development, setup and supportExperience in Reliablity flow development for EMIR tools Totem/Voltus-FI and some internal point tools support.Hands on experience in Calibre LVS and DRC rule decks development.Hands on experience in Analog Design of Bandgap ckts, Charge Pumps and RO ckts.Experience in qualification of PDKs, Analog/Mixed Signal reference flows.Experience in Release and Distribution of Design Kits.Experience in Regression testing and QA.Benchmark the Simulation tools like Spectre, MMSIM, HSPICE, Ultrasim.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.