Anil Chiliveri

About Anil Chiliveri

Career Objective:Physical Design Engineer.Core Competency:Well versed with Netlist - GDS II Flow.Experience of 7+ years in VLSI Physical Design.Working with HCLTech as Technical Lead since August 2024.Worked in Intel Technologies as SoC Design Engineer since March 2022 to August 2024.Worked in HCL Technologies as Lead Engineer from June 2018 to March 2022Physical Design Trainee experience in Mos-Chip Institute of Silicon Systems, Hyderabad from December 2017 to May 2018.Successfully completed 9 tape-outs on intel 14nm, 10nm,7nm, I3 and 18A technology nodes.Good at Synthesis, floor Planning, place & Route, Clock Tree Synthesis, Timing Optimization, Low Power Design Methodology, Physical Verification. Tools: ICC, ICCII, PT, Tango, ICV, Star-RC, Caliber, Design Compiler and fusion compiler.Good at Block level physical design & Block level timing closure.Good at Congestion free Floor-planning with High Macro Count.Have ability to resolve congestion and timing issues at every stage of PnR flow.Good at CTS- Skew Minimization.Good at DFM (Antenna, Redundant Via & Metal Density) & Physical Verification (DRC/LVS).Low Power Design Techniques.Timing analysis with SI and OCV.Good in developing and maintaining tcl scripts.

Experience

1. Technical Lead

   HCLTech

   Aug 2024 — Present · Bengaluru, IN

Education

• Kakatiya University, Warangal

  B.Tech, Electrical, Electronics and Communications Engineering

  2013 — 2017

• Pragathi Vidayanikethan High School

  SSC, Maths, Physics, Chemistry, Biology

• Govt. Polytechnic College

  Diploma, Electrical, Electronics and Communications Engineering

  2010 — 2013