Aniketh Esamudra Prakash
Design Verification @ Nvidia | Ex-Intel | UC Irvine Alum | VTU Alum
- Role
- Senior Asic Verification Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Aniketh Esamudra Prakash
Experienced engineer in semiconductor industry. Expertise in design verification, FPGA design, static timing analysis, power analysis, post silicon validation, performance/power optimization
Experience
Senior Asic Verification Engineer
Mar 2024 — Present · Santa Clara, CA, US
Education
RV-VLSI Design Center
Bachelor of Engineering (B.E.) - Final Year B.E. Project, Digital VLSI Front End (FPGA)
2014 — 2014
Visvesvaraya Technological University
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
2010 — 2014
UC Irvine
Master of Science in Electrical Engineering, Circuits and Devices (VLSI and Hardware)
2014 — 2016
Skills
- Physical Design
- Synopsys Primetime
- Cadence Virtuoso
- Ic Studio
- C++
- Perl
- Application-Specific Integrated Circuits (Asic)
- Object Oriented Programming
- Integrated Circuit Design
- Cmos
- Integrated Circuits (Ic)
- Layout Design
- Xilinx
- Systemverilog
- Altera Quartus
- Microsoft Office
- Vlsi
- Zigbee
- Linux
- Modelsim
- Static Timing Analysis
- Computer Architecture
- Analog
- Rtl Verification
- Rtl Design
- Debugging
- C
- Vhdl
- Simulations
- Keil
- Vpi Transmission Maker
- Microsoft Word
- Electronics
- Mixed Signal
- Testing
- Eagle Pcb
- Xilinx Ise
- Pcb Design
- Ic
- Field-Programmable Gate Arrays (Fpga)
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.