Aneeshkumar Polineni
Senior Formal Verification Engineer
- Role
- Senior Formal Verification Engineer at Astera Labs
- Location
- Kapurthala, PB, IN
- LinkedIn followers
- 500 followers
About Aneeshkumar Polineni
At Qualcomm, our team enhances modem and automotive block reliability through formal…
Experience
Senior Formal Verification Engineer
Mar 2025 — Present · Bengaluru, IN
Working on formal verification of PCIe switch scheduler, focusing on arbitration, fairness, and QoS guarantees.Specifying and proving safety, liveness, and invariants using property-based verification.Applying abstraction and state space exploration to uncover deadlocks, livelocks, and corner-case issues.Collaborating with design teams to refine micro-architecture based on formal counterexamples.
Education
Lovely Professional University
Bachelor of Technology - BTech, Electrical and Electronics Engineering
Maven silicon
Rtl Design and Verification Trainee, Vlsi
2021 — 2021
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.