Aneek Mandal

About Aneek Mandal

I am currently working as a CAD Physical Design Engineer at Qualcomm, Bangalore focusing on methodology/automation in Floorplanning, STA, PnR, PDN flows using Perl/Tcl/Python. I completed my B.Tech in Electronics and Communication Engineering from National Institute of Technology Durgapur, India in 2017 and then completed my Masters from Texas A&M University, College Station, TX in Electrical/Computer Engineering (graduated in December 2018). Being a Masters graduate in ECE, I thrive in a challenging and rewarding innovation-driven environment. My interests are mainly focused towards EDA/CAD/methodology in the timing (STA) and physical design (PD) space. My email ID is: a••••••••@gmail.comTechnical Skills:Tools/Domains: Cadence Virtuoso, Innovus, Calibre DRC, LVS, Cadence Spectre, Synopsys Primetime, VLSI CAD, Physical Design/STA, PDN, Physical VerificationProgramming and Scripting Languages: Perl, Tcl, C, Python, Makefile, ShellVersion control systems : Methodics/Perforce, Cliosoft/SOS

Experience

1. Senior Lead Engineer

   Qualcomm

   Jun 2024 — Present · Bangalore Urban, IN

   CAD Physical Design AutomationWorking on automation/methodology in several domains of mixed-signal IP Physical Design, including fe/edi flows, STA, PV and EMIR/PDN, which are being used for signing-off/review/debug on a lot of critical chips across multiple business units.

Education

• Texas A&M University

  Master of Engineering - MEng, Electrical and Computer Engineering

• National Institute of Technology Durgapur

  Bachelor of Technology (B.Tech.), Electronics and Communication Engineering

  2013 — 2017

Skills

• Calculations
• Mathematics
• C
• Python
• C++
• Microsoft Office
• Matlab