Anchit Arun
Verification Engineer @Scaledge Technology
Signup · Get unlimited contacts
WORK HISTORY
Verification Engineer @Scaledge Technology
EDUCATION
Indian Institute of Engineering Science and Technology (IIEST), Shibpur
Master of Technology - MTech, VLSI Design
SKILLS
ABOUT ANCHIT ARUN
3.5+ YoE in ASIC-IP and SoC level design verification Hands-on expertise in IP Verification (UVM): PMBUS Block Hands-on expertise in SOC Verification(20+ CPU Sub-System) using C-Based test cases Experience in ASIC-IP Verification: CHI Env. Development Skilled in debugging and analyzing regressions failures (tests, sequences, RTL-bugs) Experience in developing (SV & UVM) Testbench Components: Driver, Scoreboard & Checkers, Monitor Experienced in UVM RAL for register modeling, access, and verification in ASIC-IP environment Good knowledge of AMBA: APB, AHB, AXI3, CHI(Basic) Good knowledge of Coverage(Code & Functional) Analysis, CRV(Constraint) and Assertions Good knowledge of Digital Electronics, Computer Architecture and Cache Coherency Basic understanding in DFT concepts (ATPG, stuck-at faults, controllability, observability), M.Tech (VLSI) 8+ months as MT/Product Engineer in embedded medical electronics domain
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.