Anchit Arun
Design Verification Engineer, Scaledge India | MTech-VLSI Design@NIT, Shibpur(IIEST) | SoC(Multiple CPUs Subsystem) | AMBA(APB AHB AXI CHI) | UVM | SV |Python | Verilog | Embedded-C
- Role
- Verification Engineer at Scaledge Technology
- Location
- Dhanbad, JH, IN
- LinkedIn followers
- 500 followers
About Anchit Arun
3.5+ YoE in ASIC-IP and SoC level design verification Hands-on expertise in IP Verification (UVM): PMBUS Block Hands-on expertise in SOC Verification(20+ CPU Sub-System) using C-Based test cases Experience in ASIC-IP Verification: CHI Env. Development Skilled in debugging and analyzing regressions failures (tests, sequences, RTL-bugs) Experience in developing (SV & UVM) Testbench Components: Driver, Scoreboard & Checkers, Monitor Experienced in UVM RAL for register modeling, access, and verification in ASIC-IP environment Good knowledge of AMBA: APB, AHB, AXI3, CHI(Basic) Good knowledge of Coverage(Code & Functional) Analysis, CRV(Constraint) and Assertions Good knowledge of Digital Electronics, Computer Architecture and Cache Coherency Basic understanding in DFT concepts (ATPG, stuck-at faults, controllability, observability), M.Tech (VLSI) 8+ months as MT/Product Engineer in embedded medical electronics domain
Experience
Verification Engineer
Sep 2022 — Present
Education
Indian Institute of Engineering Science and Technology (IIEST), Shibpur
Master of Technology - MTech, VLSI Design
Skills
- Powerpoint
- Microsoft Excel
- Customer Service
- Social Media
- English
- Event Planning
- Microsoft Office
- Windows
- Microsoft Word
- Embedded Systems
- C++
- C
- Time Management
- Public Speaking
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