Ananya Aggarwal
GTI @ INTEL | M.Tech in VLSI Design @ TIET | Verilog/VHDL & Tanner EDA | Python, Perl & Linux Scripting | Enthusiastic Learner in ASIC/FPGA Design | Semiconductor Technology Enthusiast
- Role
- Graduate Technical Intern at Intel
- Location
- New Delhi, DL, IN
- LinkedIn followers
- 500 followers
About Ananya Aggarwal
Hi, I’m Ananya, 1st year Mech VLSI Design student at TIET, Patiala-Skilled in…
Experience
Graduate Technical Intern
Jun 2025 — Present · Bengaluru, IN
Education
Vellore Institute of Technology
Master of Science - MS, Physics
Thapar Institute of Engineering & Technology
Master of Technology - MTech, VLSI DESIGN
Bal Bharati Public School Ganga Ram Hospital Marg
Science, PCM
2004 — 2018
Delhi University
Bachelor of Science - BS, Physical Sciences
2018 — 2021
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