Ananya V.

EMIR (PDN) Engineer || Intern @ NXP Semiconductors || M.tech ‘2025 @ Delhi Technological University (formerly DCE) || Ex- Accenture ’2022 || KIET ’2020

Role
Physical Design Engineer at Mirafra Technologies
Location
New Delhi, DL, IN
LinkedIn followers
500 followers

About Ananya V.

Education: M.Tech (Digital Design & Signal Processing), Delhi Technological University (DTU) — CGPA 8.81/10Current Role: Physical Design Engineer, Mirafra Technologies - Performing static/dynamic IR-drop & EM analysis using Cadence VoltusInternship: NXP SemiconductorsGained exposure to power grid quality checks, block level static IR & dynamic IR drop.Domain Expertise: Power Integrity (IR/EM), PDN debug, EMIR flow setup, grid analysis.Tools & Skills: RedHawk-SC, Voltus, Innovus, Genus, TCL, Python, Verilog

Experience

  1. Physical Design Engineer

    Mirafra Technologies

    Sep 2025 — Present · Noida, IN

Education

  • KIET Group of Institutions

    Bachelor of Technology - BTech, Electronics and Communications Engineering

    2016 — 2020

  • Delhi Technological University (Formerly DCE)

    Master of Technology - MTech, Electronics and Communications Engineering

    2025

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Ananya V. — Physical Design Engineer at Mirafra Technologies in New Delhi, DL, IN | Unifers